wafer level package
System in Package
Flip Chip Package
High density welding wire encapsulation
Molded Interconnect System(MIS)
WLCSP
(Bumping, Repassivation, RDL)eWLCSP
(encapsulated WLCSP)eWLB
(embedded wafer level BGA)2.5D and 3D SiP eWLB
IPD
TSV for CIS
TSV for 3D IC
Compact, high performance packages for rapidly shrinking product form factors
Proven leadership in innovative FOWLP solutions with over 1.7 Billion units shipped
Innovative 2D/2.5D/3D FOWLP packages with size, performance and cost advantages
Enhanced performance and size reduction with silicon IPDs
3D TSV capabilities covering mid-end-of-line through backend assembly and test
.Electronic system or sub-system integrates multiple active and passive components for higher performance, functionality, processing speeds and low cost
.Leading SiP technology portfolio incorporates all the key technical building blocks
Advanced design rules for 2.5D and 3D FOWLP or SiP configurations
High density SMT with high accuracy component placement
Advanced mold tech for complex topography SiP applications
Highly automated process modules
Tight process control to ensure consistency and high yield
.One stop turnkey solution - wafer to fully tested SiP modules
(flip chip package-on-package)
(flip chip package-on-package)
(FCOL)
(flip chip on Molded interconnect System)
Patented fcCuBE : proven low cost, high performance advanced flip chip technology
Fine pitch Cu pillar and Bond-on-Lead (BOL) interconnection for higher routing density at a lower cost Scalability to finer bump pitches, higher I/O and advanced fab nodes at a lower cost
High speed fcBGA-H offering for network/communication market fcPoP and hybrid flip chip + wirebond configurations for increased functional integration in a smaller form factor, and Pre-stacking of memory on logic for PoP packages
Leadership in low cost substrate technologies – Embedded Trace Substrate (ETS), Molded Interconnect System (MIS) and Single Layer laminate substrate
(Side by Side,Stached Die)
Advanced wirebond technology in a cost competitive manufacturing location
Comprehensive range of single die, multi die, thermally enhanced and stacked die packages
Thin outline LGA suitable for high performance and/or portable applications
Low profile PoP provides flexibility in mixing and matching IC technologies in a thin package
Innovative process capabilities to enable MEMS and sensors chipset integration and fusion
Cost effective package approach for memory card formats
Extensive experience in leadframe and discrete packages for a wide range of applications
Patented FCOL on MIS lead frame offers leading-edge QFN package for proven better
electrical and thermal performance, particularly in power management applications
Ultra small, thin technology achieves product miniaturization
Superior RF, electrical, thermal and reliability performance
Fine line routing for high density I/O
Supports a wide range of wirebond, flip chip, SiP and PoP package configurations
Proven substrate technology with over 1B units shipped since 2010